Methods of forming a plurality of capacitors

ABSTRACT

A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive metal nitride-comprising material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Inner sidewalls of the conductive material within the trench are annealed in a nitrogen-comprising atmosphere. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area. The conductive material within the array area is incorporated into a plurality of capacitors.

RELATED PATENT DATA

This patent resulted from a continuation application of U.S. patent application Ser. No. 12/857,159, filed Aug. 16, 2010, entitled “Methods of Forming a Plurality of Capacitors”, naming Vishwanath Bhat and Kevin R. Shea as inventors, which resulted from a continuation application of U.S. patent application Ser. No. 11/711,232, filed Feb. 26, 2007, entitled “Methods of Forming a Plurality of Capacitors”, naming Vishwanath Bhat and Kevin R. Shea as inventors, now U.S. Pat. No. 7,785,962, the disclosures of which are incorporated by reference.

TECHNICAL FIELD

Embodiments herein relate to methods of forming a plurality of capacitors.

BACKGROUND

Capacitors are one type of component used in the fabrication of integrated circuits. One manner of fabricating capacitors is to initially form an insulative material (i.e., silicon dioxide doped with one or both of phosphorus and boron) within which a capacitor storage node electrode is formed. An array of openings for individual capacitors is fabricated in such insulative material, for example by etching. It is often desirable to etch away most if not all of the insulative material after individual capacitor electrodes have been formed within the openings therein. Such enables outer sidewall surfaces of the capacitor electrodes to provide increased area and thereby increased capacitance for the capacitors being formed. However, the capacitor electrodes formed in deep openings are often much taller than they are wide. This can lead to toppling of the capacitor electrodes either during the etch to expose the outer sidewalls surfaces, during transport of the substrate, and/or during deposition of the capacitor dielectric layer or the outer capacitor electrode layer. U.S. Pat. No. 6,667,502 teaches the provision of a brace or retaining structure intended to alleviate such toppling.

One manner of fabricating capacitors forms an array of capacitors within a capacitor array area. Control or other circuitry area is displaced from the capacitor array area, with the substrate including an intervening area between the capacitor array area and the control or other circuitry area. In some instances, a trench is formed in the intervening area between the capacitor array area and the other circuitry area. Such trench can be formed commensurate with the fabrication of the openings within the capacitor array area within which the isolated capacitor electrodes will be received.

When etching the material within which the capacitor electrodes are received to expose outer sidewall surfaces thereof, it may be desired that none of such material within the other circuitry area be etched. One prior art method restricts such by masking the peripheral circuitry area. Specifically, a silicon nitride layer is formed over the predominately insulative material within which the capacitor electrodes are formed. The conductive material deposited to form the capacitor electrodes within the electrode openings also deposits and lines the trench between the capacitor array area and the peripheral circuitry area. Example conductive materials include conductive metal nitrides, such as titanium nitride. The titanium nitride is polished back at least to the silicon nitride layer, thereby forming isolated container-shaped structures within individual capacitor electrode openings in the array area and within the trench. Accordingly, the sidewalls and bottom of the trench are covered or masked with titanium nitride, whereas the top or elevationally outermost surface of the peripheral or other circuitry area is covered with silicon nitride.

Etch access openings are then formed at spaced intervals in the silicon nitride within the capacitor array area to expose the insulative material within which the capacitor electrodes were formed. Elevationally outermost surfaces of the peripheral circuitry area are kept entirely masked with the silicon nitride layer. When the insulative material comprises phosphorus and/or boron doped silicon dioxide, an aqueous etching chemistry utilized to etch such highly selectively to titanium nitride and to silicon nitride is an aqueous HF solution. Such desirably results in exposure of the outer sidewalls of the individual capacitor electrodes while the peripheral insulative material remains masked from such etching by the overlying silicon nitride layer and from the titanium nitride within the peripheral trench.

Unfortunately, the titanium nitride may be formed in a manner which produces cracks or pinholes that extend laterally therethrough. This is not problematic within the capacitor array area as it is desired that any insulative material be removed from both the inner and outer lateral sidewalls of the capacitor electrodes. Passage of liquid etchant through any cracks or pinholes within the array area does not defeat this purpose. However, cracks or pinholes in the titanium nitride layer protecting the lateral sidewalls of the peripheral circuitry insulative material can be problematic. Specifically, etchant seeping therethrough can cause etching which forms voids or pockets laterally within the peripheral circuitry insulative material. These can later create fatal contact-to-contact shorts in the peripheral circuitry area when conductive vertical contacts are formed therein.

One solution to such problem is to deposit a very thin polysilicon layer to line internal portions of the capacitor electrodes and against the titanium nitride layer which laterally covers the insulative material of the peripheral circuitry area. Polysilicon is highly resistant to etch by HF. Such will shield any pinholes, thereby precluding HF or other etchants from seeping therethrough and undesirably etching the peripheral circuitry area insulative material.

Polysilicon is undesired subsequently, and is therefore removed. Accordingly, after etching back the insulative material to expose the outer sidewalls of the capacitor electrodes, a dedicated wet etch is conducted to highly selectively remove the polysilicon relative to undoped silicon dioxide, the titanium nitride, and the silicon nitride. Prior to this, a separate dedicated wet etch is conducted to remove an undesired native oxide which forms over the polysilicon.

While some embodiments disclosed herein were motivated in addressing the above identified issues, the disclosure is in no way so limited.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments of the invention are described below with reference to the following accompanying drawings.

FIG. 1 is a diagrammatic cross section of a substrate fragment in process in accordance with an embodiment of the invention.

FIG. 2 is a diagrammatic top plan view of a larger scale portion of the FIG. 1 substrate.

FIG. 3 is a view of the FIG. 1 substrate at a processing step subsequent to that shown by FIG. 1, and taken through line 3-3 in FIG. 4.

FIG. 4 is a diagrammatic top plan view of the FIG. 3 substrate fragment.

FIG. 5 is a view of the FIG. 3 substrate at a processing step subsequent to that shown by FIG. 3.

FIG. 6 is a view of the FIG. 5 substrate at a processing step subsequent to that shown by FIG. 5.

FIG. 7 is a view of the FIG. 6 substrate at a processing step subsequent to that shown by FIG. 6.

FIG. 8 is a view of the FIG. 7 substrate at a processing step subsequent to that shown by FIG. 7.

FIG. 9 is an enlarged view of a portion of the FIG. 8 substrate fragment.

FIG. 10 is a view of an alternate embodiment substrate fragment to that depicted by FIG. 9.

FIG. 11 is a view of the FIG. 8 substrate at a processing step subsequent to that shown by FIG. 9, and taken through line 11-11 in FIG. 12.

FIG. 12 is a diagrammatic top plan view of the FIG. 11 substrate fragment.

FIG. 13 is a view of the FIG. 11 substrate at a processing step subsequent to that shown by FIG. 11.

FIG. 14 is a view of the FIG. 13 substrate at a processing step subsequent to that shown by FIG. 13.

FIG. 15 is a diagrammatic representation of DRAM circuitry.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Example methods of forming pluralities of capacitors are described with reference to FIGS. 1-15. Referring initially to FIGS. 1 and 2, a substrate, in one embodiment a semiconductor substrate, is indicated generally with reference numeral 10. In the context of this document, the term “semiconductor substrate” or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Accordingly, and by way of example only, FIG. 1 might comprise a bulk semiconductor material (not shown), for example bulk monocrystalline, and/or comprise semiconductor-on-insulator layers.

Substrate 10 may be considered as comprising a capacitor array area 25, a circuitry area 75 other than capacitor array area 25, and an intervening area 50 between capacitor array area 25 and circuitry area 75. In the depicted embodiment, intervening area 50 completely surrounds and encircles capacitor array area 25 (FIG. 2), and circuitry area 75 comprises a peripheral circuitry area to that of capacitor array area 25. Alternate constructions are contemplated, of course, for example whereby neither intervening area 50 nor circuitry area 75 completely or partially encircles a capacitor array area 25.

FIG. 1 depicts an insulative material 12 having electrically conductive storage node pillars 14 formed therethrough. Materials 12 and 14 may be fabricated over some suitable underlying material, for example bulk monocrystalline and/or underlying circuitry. An example insulative material 12 includes doped and undoped silicon dioxides, for example silicon dioxide deposited by the decomposition of tetraethylorthosilicate (TEOS) and/or borophosphosilicate glass (BPSG), and/or silicon nitride. Alternately by way of example only, material 12 might comprise anisotropically etched insulative sidewall spacers, for example formed about transistor gate lines (not shown). An example material 14 is conductively doped polysilicon. Conductive material 14 can be considered as comprising or defining a plurality of capacitor storage node locations 15, 16, 17, and 18 on substrate 10. Storage node locations 15, 16, 17, and 18 are examples only, and regardless, may be conductive at this point in the process or made conductive subsequently.

An example layer 22 has been formed over material 12 and capacitor storage node locations 15, 16, 17, and 18. An example material for layer 22 comprises silicon nitride and/or undoped silicon dioxide deposited to an example thickness range of from about 100 Angstroms to about 2,000 Angstroms. Layer 22 might be included to provide an etch stop or other function.

Some insulative material 24 is received over capacitor array area 25, circuitry area 75, and also in the depicted embodiment over intervening area 50. Such might be homogeneous or comprise multiple different compositions and/or layers. An example material is silicon dioxide comprising at least one of phosphorus and boron, for example BPSG, borosilicate glass (BSG), and/or phosphosilicate glass (PSG). An example thickness range for material 24 is from about 5,000 Angstroms to about 10 microns, with 2 microns being a specific example. Thinner and greater thicknesses may also be used.

A silicon nitride-comprising layer 26 is received over insulative material 24. Such may comprise, consist essentially of, or consist of silicon nitride. An example thickness range is from about 200 Angstroms to about 5,000 Angstroms. Some or all of layer 26 might be removed, or some or all of layer 26 might remain over the substrate as part of finished circuitry construction incorporating a plurality of capacitors being fabricated. Material other than silicon nitride might also be utilized, and not all embodiments necessarily require a silicon nitride-comprising or masking layer 26.

Referring to FIGS. 3 and 4, a plurality of capacitor electrode openings 28 have been formed within silicon nitride-comprising layer 26, insulative material 24, and layer 22 over individual capacitor storage node locations 15, 16, 17, and 18. Further, a trench 30 has been formed in intervening area 50 within materials 26, 24, and 22. In one example embodiment, trench 30 completely surrounds capacitor area 25. An example technique for forming capacitor electrode openings 28 and trench 30 comprises photolithographib patterning and selective anisotropic dry etching to produce the example FIGS. 3 and 4 construction. An example minimum width of trench opening 30 is from about 200 Angstroms to about 5,000 Angstroms, while an example minimum width for capacitor electrode openings 28 is from about 200 Angstroms to about 5,000 Angstroms. For purposes of the continuing discussion, trench 30 may be considered as comprising sidewall portions 31 and 33, and capacitor electrode openings 28 may be considered as having sidewall portions 27.

Referring to FIG. 5, and in but one embodiment, elemental titanium 29 has been deposited in a highly selective manner largely over storage node locations 15, 16, 17, 18 and atop silicon nitride layer 26. An example manner of depositing titanium 29 is by plasma enhanced chemical vapor deposition using TiCl₄ and H₂. Some of titanium 29 may also deposit into openings 28 and 30 adjacent the tops thereof, as shown. Regardless, an example thickness for layer 29 over material 26 and material 14 is from about 100 Angstroms to about 200 Angstroms.

Referring to FIG. 6, a conductive metal nitride-comprising material 32 has been formed within capacitor electrode openings 28, and within trench 30 at least against a portion of sidewall portion 31 to less than completely fill trench 30. In the depicted example embodiment, conductive metal nitride-comprising material 32 also less than fills capacitor electrode openings 28, and lines sidewalls portions 27 of capacitor electrode openings 28. Alternately, conductive metal nitride-comprising material 32 might fill capacitor electrode openings 28. Conductive metal nitride-comprising material 32 can be considered as having inner sidewalls 40 and outer sidewalls 41 within capacitor electrode openings 28 within capacitor array area 25, and inner sidewalls 38 and outer sidewalls 39 within trench 30. Example conductive materials 32 comprise one or both of titanium nitride and tantalum nitride deposited to an example thickness from about 20 Angstroms to about 1,000 Angstroms.

In conjunction with a problem which motivated this disclosure, conductive metal nitride-comprising material 32 within trench 30 comprises some opening 34 extending laterally therethrough to insulative material 24 received over circuitry area 75. Such might be in the form of one or more pinholes, through-extending cracks, etc., with an example plurality of such openings 34 being indicated by way of example only. Example such laterally extending cracks/openings 34 are also shown within conductive metal nitride-comprising material 32 within capacitor electrode openings 28. Further, example opening/cracks 35 are shown in conductive metal nitride-comprising material 32 at the bases of openings 28 and 30. Regardless, some embodiments of the invention do however contemplate fewer or no such openings 34/35 being formed.

Referring to FIG. 7, conductive layers 32 and 29 have removed from over silicon nitride-comprising layer 26 at least to an outer surface thereof, thereby forming isolated/separate conductive capacitor electrodes within capacitor electrode openings 28 and an isolation structure within trench 30. Example manners of removal include chemical mechanical polishing and resist etch back. Any other manner of forming separate conductive capacitor electrodes within openings 28 could also of course be used, including by way of example only using photolithographic masking and etch.

Referring to FIGS. 8 and 9, inner sidewalls 38 of conductive metal nitride-comprising material 32 within trench 30 have been annealed in a nitrogen-comprising atmosphere. In the context of this document, an “atmosphere” is that volume of non-solid space over the substrate to which the substrate is exposed. In the context of this document, a “nitrogen-comprising atmosphere” or an “atmosphere comprising nitrogen” is an atmosphere that contains at least some non-solid nitrogen atom-containing material. By way of examples only, examples include NH₃, N₂, and N₂H₄, including any combinations thereof. In one embodiment, separate capacitor electrodes of material 32 within capacitor electrode openings 28 have also been annealed while annealing inner sidewalls 38 of material 32 within trench 30. In one embodiment, the nitrogen-comprising atmosphere directly contacts against the conductive metal nitride-comprising material during the annealing (i.e., such is not prevented from direct contact by a material through which the atmosphere cannot diffuse). In one embodiment, the annealing comprises incorporating some of the nitrogen in the nitrogen-comprising atmosphere into the conductive metal nitride-comprising material during the annealing. Example embodiments also include providing the atmosphere in any one or combinations of gas, plasma, or liquid during the annealing. In one embodiment, the nitrogen-comprising atmosphere comprises N₂. In one embodiment, the nitrogen-comprising atmosphere comprises N₂ and a temperature of at least 700° C., and perhaps at least 800° C. In one embodiment, the nitrogen-comprising atmosphere comprises plasma (i.e., generated one or both of externally of the chamber in which the substrate is received and internally within such chamber).

In one embodiment, the nitrogen-comprising atmosphere is substantially devoid of non-solid silicon-comprising material. In the context of this document, a “silicon-comprising material” is any material that contains silicon atoms. In the context of this document, “substantially devoid of non-solid silicon-comprising material” defines a quantity of non-solid silicon-comprising material from zero up to any amount that results in no detectable deposition of any material containing silicon onto the substrate during the annealing.

In one embodiment, the nitrogen-comprising atmosphere is substantially devoid of non-solid oxygen-comprising material. In the context of this document, an “oxygen-comprising material” is any material that contains oxygen atoms. In the context of this document, “substantially devoid of non-solid oxygen-comprising material” defines a quantity of non-solid oxygen-comprising material from zero up to any amount that results in no detectable deposition of any material containing oxygen onto the substrate during the annealing.

By way of examples only, embodiments for the nitrogen-comprising atmosphere annealing include temperature ranges from about 400° to about 800°, no greater than 850° C., from about 550° C. to about 650° C. (with 600° C. being a specific example), and pressure which is subatmospheric for example ranging from about 1 Torr to about 10 Torr and from about 2 Torr to about 5 Torr. Example flow of one of more nitrogen-comprising gases to a chamber within which the substrate is received during the annealing is from about 1,000 sccm to about 5,000 seem. An example time range for the annealing is from about 5 minutes to 60 minutes. Of course, values outside these ranges and limits are also contemplated.

In one embodiment, the annealing comprises rapid thermal processing (RTP) with a temperature ramp rate of at least 75° C./second. Prior art processing of a substrate comprising an array of capacitors within a capacitor array area includes a threshold voltage adjust RTP anneal for field effect devices at a temperature ramp rate of at least 75° C./second to a temperature of about 710° C. for a total period of time of about 20 seconds. A nitrogen-comprising atmosphere anneal as disclosed herein may be combined with, or effectively also includes, a threshold voltage adjust RTP anneal for field effect devices.

In one embodiment, the annealing within a nitrogen-comprising atmosphere is effective to close-off a laterally extending opening with conductive metal nitride-comprising material. FIGS. 8-9 depict one example such embodiment. Such shows conductive metal nitride-comprising layer 32 within trench 30 as comprising a thickness or length “L” (FIG. 9) through layer 32 along which opening/crack 34 extends. In one embodiment and as shown in FIGS. 8 and 9, the annealing has been effective to only partially extend conductive metal nitride-comprising material within the depicted opening 34 along an entirety of opening/crack length L. Another example embodiment substrate fragment 10 a is shown in FIG. 10. Like numerals form the first-described embodiment are utilized where appropriate, with differences being indicated with the suffix “a”. In FIG. 10, the annealing has been effective to fully extend conductive metal nitride-comprising material within the depicted opening 34 along the entirety of opening/crack length L.

Referring to FIGS. 11 and 12, etch openings 45 have been formed through first silicon nitride-comprising layer 26 within capacitor array area 25 effective to expose insulative material 24 within capacitor array area 25 while leaving the elevationally outermost surfaces of insulative material 24 within circuitry area 75 completely covered with first silicon nitride-comprising layer 26. Such provide access for etchant to get to and etch material 24 within capacitor array area 25. In the above described embodiment, the annealing in a nitrogen-comprising atmosphere was conducted prior to forming etch openings 45. In one embodiment, the annealing in a nitrogen-comprising atmosphere is conducted after forming etch openings 45.

Referring to FIG. 13, insulative material 24 within capacitor array area 25 has been etched with a liquid etching solution effective to expose outer sidewall portions of outer sidewalls 41 of conductive metal nitride-comprising material 32 within capacitor array area 25. An example liquid etchant solution is aqueous, and regardless for example comprising HF. One example solution comprises from 5:1 to 20:1 water to I-IF by volume, wherein said HF is a 49 weight percent solution of HF in water. An example etching temperature is room ambient, with an example etching pressure also being room ambient. However, temperatures and pressures below and above room ambient are also contemplated. By way of example only, a 10:1 by volume water to HF solution per the above can be used to etch PSG at a rate of approximately from 5,000 Angstroms/minute to 15,000 Angstroms/minute, while etching a layer consisting essentially of silicon nitride at a rate of from 20 Angstroms/minute to 80 Angstroms/minute. By way of example only, additional example HF-containing solutions might contain any one or combination of HNO₃, acetic acid, NH₄F, and proprionic acid.

Conductive metal nitride-comprising material 32 within capacitor array area 25 is incorporated into a plurality of capacitors. For example, FIG. 14 depicts the deposition of a capacitor dielectric layer 60. By way of example only, an example material is a silicon dioxide, silicon nitride, silicon dioxide composite, or any suitable high k dielectric, whether existing or yet-to-be developed. Example high k dielectrics include Ta₂O₅ and barium strontium titanate.

An outer capacitor electrode layer 70 has been deposited over capacitor dielectric layer 60, thereby defining capacitors 81, 82, 83, and 84. Such are depicted as comprising a common cell capacitor plate to all of the depicted capacitors, for example as might be utilized in DRAM or other circuitry. For example and by way of example only, FIG. 15 depicts an example DRAM cell incorporating capacitor 81. Such comprises an example transistor gate wordline 87 having insulative sidewall spacers, an insulative cap and a conductive region under the cap such as a silicide, a conductive polysilicon region under the silicide, and a gate dielectric region under the polysilicon. Source/drain regions 80 are shown formed within semiconductive material operatively proximate wordline 87. One of such electrically connects with capacitor 81, and another such electrically connects with a bitline 85.

The above-described embodiment depicts at least some of silicon nitride masking layer 26 remaining as part of the finished circuitry construction. Alternate bracing structures might be utilized. Alternately, no bracing might be utilized during processing or in the final construction.

Conducting an anneal in an NH₃-comprising atmosphere of the substrate of FIG. 6 (i.e., prior to forming separate capacitor electrodes within the openings) where material 32 was TiN increased resulting defects/decreased resulting yield in comparison with substrates identically processed but for an NH₃-comprising atmosphere anneal of the FIG. 6 substrate. It is theorized that such an anneal may be increasing stress within the TiN layer prior to separation to form individual/separated capacitor electrodes. In light thereof, surprisingly conducting an anneal in accordance with embodiments of the invention disclosed herein (after forming separate capacitor electrodes) may reduce resulting defects/increase yield in comparison with substrates otherwise identically processed but for an anneal in accordance with embodiments of the invention disclosed herein, and regardless of whether a nitrogen-comprising atmosphere anneal is conducted of the FIG. 6 substrate. Conducting an anneal in accordance with embodiments of the invention disclosed herein after formation of separate capacitor electrodes may be relaxing or reducing stress within the conductive metal nitride-comprising material without necessarily causing reflow of such material.

In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents. 

1. A method of forming a plurality of capacitors, comprising: providing a substrate comprising a capacitor array area and another circuitry area other than the capacitor array area, an insulative material received over the capacitor array area and the other circuitry area, the capacitor array area comprising a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations, the other circuitry area comprising a sidewall of the insulative material; forming conductive metal nitride-comprising material within the capacitor electrode openings within the capacitor array area and against at least a portion of said sidewall of insulative material; annealing the conductive metal nitride-comprising material received against said portion of said sidewall of insulative material in a nitrogen-comprising atmosphere, the nitrogen-comprising atmosphere being devoid of non-solid oxygen-comprising material; after the annealing, etching the insulative material within the capacitor array area to expose outer sidewall portions of the conductive metal nitride-comprising material within the capacitor array area; and after the etching, incorporating the conductive metal nitride-comprising material within the capacitor array into a plurality of capacitors that comprise the conductive metal nitride-comprising material within the capacitor array.
 2. The method of claim 1 wherein the nitrogen-comprising atmosphere comprises NH₃.
 3. The method of claim 1 wherein the nitrogen-comprising atmosphere comprises N₂H₄.
 4. The method of claim 1 wherein the nitrogen-comprising atmosphere comprises N₂ and a temperature of at least 700° C.
 5. The method of claim 1 wherein the conductive metal nitride-comprising material against at least a portion of said sidewall comprises an opening extending laterally therethrough to the insulative material received over the other circuitry area prior to the annealing, the annealing being effective to close-off the laterally extending opening.
 6. The method of claim 1 wherein the insulative material comprises silicon dioxide comprising at least one of phosphorus and boron, and the liquid etching solution comprises HF.
 7. The method of claim 1 wherein the forming lines sidewall portions of the capacitor electrode openings with the conductive metal nitride-comprising material which less than fills the capacitor electrode openings.
 8. The method of claim 1 wherein the annealing comprises contacting the nitrogen-comprising atmosphere directly against the conductive metal nitride-comprising material during the annealing.
 9. The method of claim 1 wherein the annealing comprises incorporating some of the nitrogen in the nitrogen-comprising atmosphere into the conductive metal nitride-comprising material during the annealing.
 10. The method of claim 5 wherein the laterally extending opening has a length through the conductive metal nitride-comprising material, the annealing been effective to only partially extend conductive metal nitride-comprising material along an entirety of the length.
 11. The method of claim 5 wherein the laterally extending opening has a length through the conductive metal nitride-comprising material, the annealing been effective to fully extend conductive metal nitride-comprising material along an entirety of the length.
 12. The method of claim 5 wherein the nitrogen-comprising atmosphere is liquid.
 13. The method of claim 5 wherein the nitrogen-comprising atmosphere comprises gas.
 14. A method of forming a plurality of capacitors, comprising: providing a substrate comprising a capacitor array area and another circuitry area other than the capacitor array area, an insulative material received over the capacitor array area and the other circuitry area, the capacitor array area comprising a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations, the other circuitry area comprising a sidewall of the insulative material; forming conductive metal nitride-comprising material within the capacitor electrode openings within the capacitor array area and against at least a portion of said sidewall of insulative material; annealing the conductive metal nitride-comprising material received against said portion of said sidewall of insulative material in a nitrogen-comprising atmosphere, the nitrogen-comprising atmosphere comprising liquid; after the annealing, etching the insulative material within the capacitor array area to expose outer sidewall portions of the conductive metal nitride-comprising material within the capacitor array area; and after the etching, incorporating the conductive metal nitride-comprising material within the capacitor array into a plurality of capacitors that comprise the conductive metal nitride-comprising material within the capacitor array.
 15. A method of forming a plurality of capacitors, comprising: providing a substrate comprising a capacitor array area and another circuitry area other than the capacitor array area, an insulative material received over the capacitor array area and the other circuitry area, the capacitor array area comprising a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations, the other circuitry area comprising a sidewall of the insulative material; forming conductive metal nitride-comprising material within the capacitor electrode openings within the capacitor array area and against at least a portion of said sidewall of insulative material; annealing the conductive metal nitride-comprising material received against said portion of said sidewall of insulative material in a nitrogen-comprising atmosphere; after the annealing, etching the insulative material within the capacitor array area to expose outer sidewall portions of the conductive metal nitride-comprising material within the capacitor array area; and after the etching, incorporating the conductive metal nitride-comprising material within the capacitor array into a plurality of capacitors that comprise the conductive metal nitride-comprising material within the capacitor array.
 16. The method of claim 15 wherein the conductive metal nitride-comprising material against at least a portion of said sidewall comprises an opening extending laterally therethrough to the insulative material received over the other circuitry area prior to the annealing, the annealing being effective to close-off the laterally extending opening.
 17. The method of claim 16 wherein the laterally extending opening has a length through the conductive metal nitride-comprising material, the annealing been effective to only partially extend conductive metal nitride-comprising material along an entirety of the length.
 18. The method of claim 16 wherein the laterally extending opening has a length through the conductive metal nitride-comprising material, the annealing been effective to fully extend conductive metal nitride-comprising material along an entirety of the length.
 19. The method of claim 15 wherein the nitrogen-comprising atmosphere comprises NH₃.
 20. The method of claim 15 wherein the nitrogen-comprising atmosphere comprises N₂H₄.
 21. The method of claim 15 wherein the nitrogen-comprising atmosphere comprises N₂ and a temperature of at least 700° C.
 22. The method of claim 15 nitrogen-comprising atmosphere comprises a temperature of at least 400° C.
 23. The method of claim 15 nitrogen-comprising atmosphere comprises a temperature of no greater than 850° C.
 24. The method of claim 15 nitrogen-comprising atmosphere is subatmospheric.
 25. The method of claim 15 wherein the annealing comprises rapid thermal processing with a temperature ramp rate of at least 75° C./second. 